Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.2 (WebPack) - M.63c Target Family: Spartan3A and Spartan3AN
OS Platform: NT64 Target Device: xc3s400a
Project ID (random number) 6e960425d0804341bfba6fa29472039c.9B2ABB41063540748ED39A46A329E003.2 Target Package: ft256
Registration ID 0_0_477 Target Speed: -4
Date Generated 2010-10-18T11:38:32 Tool Flow ISE
 
User Environment
OS Name Microsoft OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz CPU Speed 3528 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=1
  • 26-bit up counter=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=6
  • AGG_IO=6
  • AGG_SLICE=13
  • NUM_4_INPUT_LUT=26
  • NUM_BONDED_IBUF=2
  • NUM_BONDED_IOB=4
  • NUM_BUFGMUX=1
  • NUM_CYMUX=25
  • NUM_LUT_RT=25
  • NUM_SLICEL=13
  • NUM_SLICE_FF=26
  • NUM_XOR=26
 		NetStatistics
  • NumNets_Active=47
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=13
  • NumNodesOfType_Active_CNTRLPIN=13
  • NumNodesOfType_Active_DOUBLE=22
  • NumNodesOfType_Active_DUMMY=27
  • NumNodesOfType_Active_DUMMYESC=2
  • NumNodesOfType_Active_GLOBAL=6
  • NumNodesOfType_Active_HUNIHEX=3
  • NumNodesOfType_Active_INPUT=43
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=30
  • NumNodesOfType_Active_OUTPUT=39
  • NumNodesOfType_Active_VFULLHEX=1
  • NumNodesOfType_Active_VUNIHEX=3
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_VCCOUT=1
 SiteStatistics
  • IBUF-DIFFMLR=1
  • IBUF-DIFFMTB=1
  • IOB-DIFFMLR=1
  • IOB-DIFFMTB=1
  • IOB-DIFFSLR=2
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=2
  • IBUF_DELAY_ADJ_BBOX=2
  • IBUF_INBUF=2
  • IBUF_PAD=2
  • IOB=4
  • IOB_OUTBUF=4
  • IOB_PAD=4
  • SLICEL=13
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=13
  • SLICEL_CYMUXG=12
  • SLICEL_F=13
  • SLICEL_FFX=13
  • SLICEL_FFY=13
  • SLICEL_G=13
  • SLICEL_GNDF=12
  • SLICEL_GNDG=12
  • SLICEL_XORF=13
  • SLICEL_XORG=13
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:2]
  • IBUF_DELAY_VALUE=[DLY0:2]
  • IFD_DELAY_VALUE=[DLY0:2]
  • SEL_IN=[SEL_IN:2] [SEL_IN_INV:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS33:2]
 IOB
  • O1=[O1_INV:0] [O1:4]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:4]
  • SUSPEND=[3STATE:4]
 IOB_PAD
  • DRIVEATTRBOX=[12:4]
  • IOATTRBOX=[LVCMOS33:4]
  • SLEW=[SLOW:4]
 SLICEL
  • BX=[BX_INV:0] [BX:1]
  • CE=[CE:0] [CE_INV:13]
  • CIN=[CIN_INV:0] [CIN:12]
  • CLK=[CLK:13] [CLK_INV:0]
 SLICEL_CYMUXF
  • 0=[0:13] [0_INV:0]
  • 1=[1_INV:0] [1:13]
 SLICEL_CYMUXG
  • 0=[0:12] [0_INV:0]
 SLICEL_FFX
  • CE=[CE:0] [CE_INV:13]
  • CK=[CK:13] [CK_INV:0]
  • D=[D:13] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:13]
  • FFX_SR_ATTR=[SRLOW:13]
  • LATCH_OR_FF=[FF:13]
  • SYNC_ATTR=[ASYNC:13]
 SLICEL_FFY
  • CE=[CE:0] [CE_INV:13]
  • CK=[CK:13] [CK_INV:0]
  • D=[D:13] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:13]
  • FFY_SR_ATTR=[SRLOW:13]
  • LATCH_OR_FF=[FF:13]
  • SYNC_ATTR=[ASYNC:13]
 SLICEL_XORF
  • 1=[1_INV:0] [1:13]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IBUF
  • I=2
  • PAD=2
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=2
  • SEL_IN=2
 IBUF_INBUF
  • IN=2
  • OUT=2
 IBUF_PAD
  • PAD=2
 IOB
  • O1=4
  • PAD=4
 IOB_OUTBUF
  • IN=4
  • OUT=4
 IOB_PAD
  • PAD=4
 SLICEL
  • BX=1
  • CE=13
  • CIN=12
  • CLK=13
  • COUT=12
  • F1=13
  • G1=13
  • XQ=13
  • YQ=13
 SLICEL_C1VDD
  • 1=1
 SLICEL_CYMUXF
  • 0=13
  • 1=13
  • OUT=13
  • S0=13
 SLICEL_CYMUXG
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
 SLICEL_F
  • A1=13
  • D=13
 SLICEL_FFX
  • CE=13
  • CK=13
  • D=13
  • Q=13
 SLICEL_FFY
  • CE=13
  • CK=13
  • D=13
  • Q=13
 SLICEL_G
  • A1=13
  • D=13
 SLICEL_GNDF
  • 0=12
 SLICEL_GNDG
  • 0=12
 SLICEL_XORF
  • 0=13
  • 1=13
  • O=13
 SLICEL_XORG
  • 0=13
  • 1=13
  • O=13
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400a-ft256-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400a-ft256-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400a-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400a-ft256-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400a-ft256-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400a-ft256-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400a-ft256-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
bitgen 2 2 0 0 0 0 0
edif2ngd 5 5 0 0 0 0 0
map 4 4 0 0 0 0 0
netgen 5 5 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngcbuild 5 5 0 0 0 0 0
ngdbuild 11 11 0 0 0 0 0
par 4 4 0 0 0 0 0
trce 4 4 0 0 0 0 0
xst 14 13 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/cgn_c_df_hdl_implement_design.htm ( 1 ) /doc/usenglish/isehelp/cgn_c_df_ise_flow.htm ( 1 )
/doc/usenglish/isehelp/cgn_c_df_schematic_flow.htm ( 1 ) /doc/usenglish/isehelp/cgn_c_df_synthesize_verilog_design.htm ( 1 )
/doc/usenglish/isehelp/cgn_c_df_verilog_behavioral_sim.htm ( 1 ) /doc/usenglish/isehelp/cgn_c_df_verilog_create_test_bench.htm ( 1 )
/doc/usenglish/isehelp/cgn_c_df_verilog_flow.htm ( 1 ) /doc/usenglish/isehelp/cgn_c_df_verilog_instantiate_cores.htm ( 1 )
/doc/usenglish/isehelp/cgn_c_df_vhdl_flow.htm ( 1 ) /doc/usenglish/isehelp/cgn_c_overview.htm ( 1 )
/doc/usenglish/isehelp/cgn_p_add_ip_projnav_design.htm ( 1 ) /doc/usenglish/isehelp/cgn_p_adding_generated_ip_design_verilog_flow.htm ( 1 )
/doc/usenglish/isehelp/cgn_p_adding_generated_ip_design_vhdl_flow.htm ( 1 ) /doc/usenglish/isehelp/cgn_p_create_project.htm ( 1 )
/doc/usenglish/isehelp/cgn_r_architecture_support.htm ( 1 ) /doc/usenglish/isehelp/cgn_r_shortcuts.htm ( 1 )
/doc/usenglish/isehelp/cgn_r_toolbar.htm ( 1 ) /doc/usenglish/isehelp/cgn_r_window.htm ( 1 )
/doc/usenglish/isehelp/ism_c_modes_operation_overview.htm ( 1 ) /doc/usenglish/isehelp/ism_c_os_support.htm ( 1 )
/doc/usenglish/isehelp/ism_c_overview.htm ( 2 ) /doc/usenglish/isehelp/ism_c_predefined_xilinx_sim_macro.htm ( 1 )
/doc/usenglish/isehelp/ism_c_steps_compile_design.htm ( 1 ) /doc/usenglish/isehelp/ism_c_steps_debug_design.htm ( 1 )
/doc/usenglish/isehelp/ism_c_steps_examine_design.htm ( 1 ) /doc/usenglish/isehelp/ism_c_steps_files_libraries.htm ( 1 )
/doc/usenglish/isehelp/ism_c_steps_overview.htm ( 1 ) /doc/usenglish/isehelp/ism_c_steps_simulate_design.htm ( 1 )
/doc/usenglish/isehelp/ism_c_verilog_sim_overview.htm ( 1 ) /doc/usenglish/isehelp/ism_c_verilog_supporting_libraries.htm ( 1 )
/doc/usenglish/isehelp/ism_c_wave_view_overview.htm ( 1 ) /doc/usenglish/isehelp/ism_db_clock.htm ( 1 )
/doc/usenglish/isehelp/ism_p_saving_wave_configuration.htm ( 1 ) /doc/usenglish/isehelp/ism_r_adding_signals_wave_set.htm ( 1 )
/doc/usenglish/isehelp/ism_r_creating_new_wave_set.htm ( 1 ) /doc/usenglish/isehelp/ism_r_interactive_sim_cl.htm ( 1 )
/doc/usenglish/isehelp/ism_r_library_mapping_file.htm ( 1 ) /doc/usenglish/isehelp/ism_r_p_opening_closing_wave_config.htm ( 1 )
/doc/usenglish/isehelp/ism_r_running_verilog_functional_sim_cl.htm ( 1 ) /doc/usenglish/isehelp/ism_r_running_verilog_timing_sim_cl.htm ( 1 )
/doc/usenglish/isehelp/ism_r_search_order_verilog_design.htm ( 1 ) /doc/usenglish/isehelp/ism_r_tutorial.htm ( 1 )
/doc/usenglish/isehelp/ism_r_whats_new.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/simple_counter_tbw PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2010-10-17T10:38:04 PROP_intWbtProjectID=9B2ABB41063540748ED39A46A329E003
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.simple_counter_tbw PROP_xilxBitgCfg_GenOpt_Compress=true
PROP_AutoTop=true PROP_DevFamily=Spartan3A and Spartan3AN
PROP_DevDevice=xc3s400a PROP_DevFamilyPMName=spartan3a
PROP_ISimSimulationRunTime_behav_tb=2000 ns PROP_DevPackage=ft256
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=2
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDE=26 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=25 NGDBUILD_NUM_MUXCY=25 NGDBUILD_NUM_OBUF=4
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDE=26 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=25 NGDBUILD_NUM_MUXCY=25
NGDBUILD_NUM_OBUF=4 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
 
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=171 ms, 18532 KB
Total Signals=15
Total Nets=17
Total Blocks=3
Total Processes=13
Total Simulation Time=2 us
Simulation Resource Usage=0.187201 sec, 470990 KB
Simulation Mode=gui
Hardware CoSim=0