simple_count Project Status (10/18/2010 - 11:19:18)
Project File: blink_led.xise Parser Errors: No Errors
Module Name: simple_count Implementation State: Programming File Generated
Target Device: xc3s400a-4ft256
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 26 7,168 1%  
Number of 4 input LUTs 1 7,168 1%  
Number of occupied Slices 13 3,584 1%  
    Number of Slices containing only related logic 13 13 100%  
    Number of Slices containing unrelated logic 0 13 0%  
Total Number of 4 input LUTs 26 7,168 1%  
    Number used as logic 1      
    Number used as a route-thru 25      
Number of bonded IOBs 6 195 3%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 1.74      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentlun. 18. oct. 11:17:20 2010000
Translation ReportCurrentlun. 18. oct. 11:17:25 2010000
Map ReportCurrentlun. 18. oct. 11:17:30 2010002 Infos (0 new)
Place and Route ReportCurrentlun. 18. oct. 11:17:50 2010000
Power Report     
Post-PAR Static Timing ReportCurrentlun. 18. oct. 11:17:54 2010004 Infos (0 new)
Bitgen ReportCurrentlun. 18. oct. 11:18:00 2010000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datelun. 18. oct. 10:37:29 2010
WebTalk ReportCurrentlun. 18. oct. 11:18:00 2010
WebTalk Log FileCurrentlun. 18. oct. 11:18:08 2010

Date Generated: 10/19/2010 - 17:28:20